1. Field of the Invention
The present invention generally relates to an ATM switch circuit for handling ATM cells and a method for controlling such an ATM switch circuit. More specifically, the present invention is directed to such an ATM switch circuit capable of increasing a use efficiency of an address memory even when a total number of output ports of this ATM switch circuit is increased, and also a control method for this ATM switch circuit.
2. Description of the Related Art
Conventionally, ATM(Asynchronous Transfer Mode) transmission apparatuses and also ATM switching apparatuses have been widely used. For instance, Japanese Patent Laid-open Application No. Hei6-62041 published in 1994 discloses the ATM transmission apparatus. That is, when the broadcast communication is carried out in the conventional ATM transmission apparatus, the entered ATM cells are temporarily stored into the memory and then the stored ATM cells are read to be outputted. The above-explained transmission apparatus and switching apparatus are equipped with an ATM switch circuit as shown in FIG. 44. That is, as represented in FIG. 44, in this conventional ATM switch circuit, the ATM cells entered via an input port 1011 through an input port 101N are multiplexed by a multiplexing circuit 101, and then the multiplexed cell is transferred to a cell buffer memory 102. The cell buffer memory 102 stores thereinto the entered cells in accordance with an empty address given from an empty address memory 107. A write control unit 104 checks output ports 1031 to 103N for outputting cells based upon a header portion of a multiplexed cell from the multiplexing unit 101. Thereafter, the write control unit 104 issues a request to the empty address management memory 107, by which an empty address used to store a cell is outputted. Also, the write control unit 104 instructs the relevant address memory to store thereinto the empty address supplied from the empty address management memory 107.
Address memories 1061 to 106N correspond to FIFO (First-In-First-Out) memories. These address memories 1061 to 106N are provided in correspondence with the above-described output ports 1031 to 103N. Then, in response to an instruction issued from the write control unit 104, these address memories 1061 to 106N store thereinto the empty address supplied from the empty address management memory 107. The empty address management memory 107 stores thereinto the empty address of the cell buffer memory 102 and manages the stored empty addresses. It should be noted that the above-described empty address corresponds to such an address that when the read control unit 105 issues a read instruction, this address is outputted from the address memory corresponding to this read instruction.
Based upon these address memories 1061 to 106N and the empty address management memory 107, the addresses of the cells outputted from the output ports 1031 to 103N are stored/managed in correspondence with the output ports 1031 to 103N. Then, when the cell is outputted, the cell buffer memory 102 reads out the stored cells in response to the addresses outputted by the address memories 1061 to 106N by receiving the instruction of the read control unit 105. Thereafter, the cells read from the cell buffer memory 102 are supplied to a separating unit 103. The separating unit 103 separates the cells supplied from the cell buffer memory 102 to supply the separated cell to the respective output ports 1031 to 103N.
However, the above-described conventional ATM switch circuit owns the following problems. That is, as indicated in FIG. 44, this conventional ATM switch circuit is equipped with the address memories 1061 to 106N in correspondence with the output ports 1031 to 103N. As a result, when the total number of the above-described output ports is increased, there is a problem that the total quantity of the above-explained address memories would be increased. Depending upon the operation conditions of the communication system equipped with the conventional ATM switch circuit, the ATM cells are frequently transmitted. As a result, there are such output ports whose use frequencies are high, and other output ports whose use frequencies are low. In this case, when the ATM switching system is arranged by employing the address memories 1061 to 106N in correspondence with the output ports 1031 to 103N, there is another problem that the use efficiency of the address memories corresponding to the output ports, the use frequencies of which are low would be lowered.
The present invention has-been made to solve the above-described problems of the conventional ATM switch circuit, and therefore, has an object to provide an ATM switch circuit capable of preventing an increase of address memories which is caused when a total number of output ports is increased, and capable of avoiding a decrease of a use efficiency of these address memories.
To achieve the object, an ATM switch circuit, according to a first aspect of the present invention, is featured by that in an ATM (Asynchronous Transfer Mode) switch circuit including: an ATM cell buffer memory for storing thereinto an ATM cell; and ATM cell managing means for issuing both a storage request for an inputted ATM cell and destination information indicative of an output port corresponding to a destination of the inputted ATM cell, and also for issuing both an output request and the destination information when the ATM cell is outputted, in which:
the inputted ATM cell is written into the cell buffer memory based upon a buffer address defined by the storage request; the written ATM cell is read out from the cell buffer memory based on another buffer address defined by the output request to thereby be transmitted to the ATM cell managing means; and upon receipt of the transmitted ATM cell, the ATM cell managing means transmits the received ATM cell to the output port in accordance with the destination information,
the ATM switch circuit is comprised of:
empty address managing means for managing an empty address of the cell buffer memory, and for outputting the empty address as a buffer address to the cell buffer memory upon receipt of the storage request issued from the ATM cell managing means; and
buffer address managing means for sequentially chaining a plurality of buffer addresses to each other when the buffer address managing means receives the storage requests issued from the ATM cell managing means and the plural buffer addresses transmitted from the empty address managing means, whereby such buffer addresses of ATM cells directed to the same output port are formed in a chain structure; and when the output request and the destination information issued from the ATM cell managing means are received, the buffer address managing means reads out the corresponding buffer address from the chain structure corresponding to the received destination information to thereby transmit the read buffer address to both the cell buffer memory and the empty address managing means.
Also, an ATM switch circuit, according to a second aspect of the present invention, is featured by that in the ATM switch circuit according to the first aspect of the present invention, the buffer address managing means includes:
a buffer address storage unit for receiving one buffer address from the empty address managing means to thereby chain the received buffer address to a succeeding buffer address, whereby the buffer addresses directed to the output port are formed in the chain structure;
a pointer storage unit for storing thereinto both a write pointer and a read pointer with respect to each of the chain structures, the write pointer pointing out a latest buffer address located at a last portion of the chain structure of the buffer address storage unit, and the read pointer pointing out a buffer address located at a head portion of the chain structure; and
a control unit for controlling the pointer storage unit to read a write pointer corresponding to the destination information and also for storing the buffer address derived from the empty address managing means into a storage area subsequent to storage areas on the output port pointed by the write pointer upon receipt of the storage request and the destination information issued from the cell managing means; and for reading a read pointer from the pointer storage unit upon receipt of the output request and the destination information issued from the cell managing means, whereby a buffer address indicative of the read pointer is transmitted to the cell buffer memory and the empty address managing means.
Also, an ATM switch circuit, according to a third aspect of the present invention, is featured by that in an ATM (Asynchronous Transfer Mode) switch circuit including: an ATM cell buffer memory for storing thereinto an ATM cell; and ATM cell managing means for issuing both a storage request for an inputted ATM cell and destination information indicative of an output port corresponding to a destination of the inputted ATM cell, and also for issuing both an output request and the destination information when the ATM cell is outputted, in which:
the inputted ATM cell is written into the cell buffer memory based upon a buffer address defined by the storage request; the written ATM cell is read out from the cell buffer memory based on another buffer address defined by the output request to thereby be transmitted to the ATM cell managing means; and upon receipt of the transmitted ATM cell, the ATM cell managing means transmits the received ATM cell to the output port in accordance with the destination information,
the ATM switch circuit is comprised of:
empty address managing means for managing an empty address of the cell buffer memory, and for outputting the empty address as a buffer address to the cell buffer memory upon receipt of the storage request issued from the ATM cell managing means; and
buffer address managing means for managing the buffer addresses in such a manner that while xe2x80x9cL (symbol xe2x80x9cLxe2x80x9d being an arbitrary natural number)xe2x80x9d pieces of storage areas capable of storing the buffer addresses are defined as one page, a chain structure is formed by chaining a plurality of the pages to each other and is made in correspondence with each of the output ports; upon receipt of the storage request issued from the cell managing means and also the buffer addresses transmitted from the empty address managing means, the received buffer addresses are sequentially stored into the storage area of the page of the chain structure; and also when the output request and the destination information issued from the ATM cell managing means are received, the buffer address managing means sequentially reads out the corresponding buffer address from the storage area of the page of chain structure corresponding to the received destination information to thereby transmit the read buffer address to both the cell buffer memory and the empty address managing means.
Also, an ATM switch circuit, according to a fourth aspect of the present invention, is featured by that in the ATM switch circuit according to the third aspect of the present invention, the buffer address managing means includes:
a buffer address storage unit for storing thereinto the buffer address derived from the empty address managing means, while the xe2x80x9cLxe2x80x9d pieces of storage areas for storing the buffer addresses are defined as one page, by chaining the pages to each other to form chain structures and also by employing the chain structures corresponding to the respective output ports;
a pointer storage unit for storing thereinto both a write pointer and a read pointer with respect to each of the chain structures, the write pointer pointing out a latest buffer address contained in a page located at a last portion of the chain structure of the buffer address storage unit, and the read pointer pointing out a first buffer address contained in a page located at a head portion of the chain structure; and
a control unit for controlling said pointer storage unit to read a write pointer corresponding to the destination information and also for storing the buffer address derived from the empty address managing means into a storage area subsequent to storage areas on the output port pointed by the write pointer upon receipt of the storage request and the destination information issued from the cell managing means; and for reading a read pointer from the pointer storage unit upon receipt of the output request and the destination information issued from the cell managing means, whereby a buffer address indicative of the read pointer is transmitted to the cell buffer memory and the empty address managing means.
Also, an ATM switch circuit, according to a fifth aspect of the present invention, is featured by comprising:
multiplexing means for producing a storage request of an inputted ATM cell and destination information indicative of an output port corresponding to the destination of the inputted ATM cell;
separating means for producing an output request and destination information when the ATM cell is outputted;
a cell buffer memory for storing thereinto the ATM cell derived from the multiplexing means, while xe2x80x9cLxe2x80x9d pieces of storage areas capable of storing the ATM cells are defined as one page, by chaining the pages to each other so as to form a chain structure and also by employing the respective chain structures corresponding to the respective output ports, and also for reading the ATM cell to send the read ATM cell to the separating means; and
cell buffer memory control means for controlling such that the ATM cells derived from the multiplexing means are sequentially stored into the chain structure corresponding to the destination information, and when the storage request and the destination produced from the multiplexing means are received, the cell buffer memory is pointed out; and also for controlling such that the ATM cells are sequentially read from the chain structure corresponding to the destination information to thereby transmit the read ATM cells to the separating means, and when both the output request and the destination information derived from the separating means are received, the cell buffer memory is pointed out.
Also, an ATM switch circuit, according to a sixth aspect of the present invention, is featured by that in the ATM switch circuit according to the fifth aspect of the present invention, the cell buffer memory control means includes:
an address storage unit for storing thereinto both a writing buffer address and a reading buffer address, the writing buffer address designating a latest ATM cell contained in a page located at a last portion of the chain structure of the cell buffer memory, and the reading buffer address designating a first ATM cell contained in another page located at a head portion of the chain structure; and
a control unit for controlling said cell buffer memory in such a manner that when the storage request and the destination information are received from the multiplexing means, the control unit reads the writing buffer address corresponding to the destination information from the address storage unit so as to control the cell buffer memory based upon the read writing buffer address, whereas when the output request and the destination information are received from said separating means, the control unit reads the reading buffer address from the address storage unit so as to control the cell buffer memory based upon the read reading buffer address.
Also, an ATM switch circuit controlling method, according to a seventh aspect of the present invention, is featured by that in a method for controlling an ATM (Asynchronous Transfer Mode) switch circuit by controlling: an ATM cell buffer memory for storing thereinto an ATM cell; and ATM cell managing means for issuing both a storage request for an inputted ATM cell and destination information indicative of an output port corresponding to a destination of the inputted ATM cell, and also for issuing both an output request and the destination information when the ATM cell is outputted, in which:
the inputted ATM cell is written into the cell buffer memory based upon a buffer address defined by the storage request; the written ATM cell is read out from the cell buffer memory based on another buffer address defined by the output request to thereby be transmitted to the ATM cell managing means; and upon receipt of the transmitted ATM cell, the ATM cell managing means transmits the received ATM cell to the output port in accordance with the destination information,
the ATM switch circuit controlling method is comprised of:
a first step for managing an empty address of the cell buffer memory, and for outputting the empty address as a buffer address to the cell buffer memory upon receipt of the storage request issued from the ATM cell managing means;
a second step for sequentially chaining a plurality of buffer addresses to each other when receiving the storage requests issued from the ATM cell managing means and the empty address as the buffer address transmitted from the first step, whereby such plural buffer addresses of ATM cells directed to the same output port are formed in a chain structure; and
a third step for reading out the corresponding buffer address from the chain structure corresponding to the received destination thereof when the output request and the destination information issued from the ATM cell managing means are received, by which the read buffer address is transmitted to the cell buffer memory, wherein:
the buffer address read at the third step is managed at the first step.
Also, an ATM switch circuit controlling method, according to an eighth aspect of the present invention, is featured by that in a method for controlling an ATM (Asynchronous Transfer Mode) switch circuit by controlling: an ATM cell buffer memory for storing thereinto an ATM cell; and ATM cell managing means for issuing both a storage request for an inputted ATM cell and destination information indicative of an output port corresponding to a destination of the inputted ATM cell, and also for issuing both an output request and the destination information when the ATM cell is outputted, in which:
the inputted ATM cell is written into the cell buffer memory based upon a buffer address defined by the storage request; the written ATM cell is read out from the cell buffer memory based on another buffer address defined by the output request to thereby be transmitted to the ATM cell managing means; and upon receipt of the transmitted ATM cell, the ATM cell managing means transmits the received ATM cell to the output port in accordance with the destination information,
the ATM switch circuit controlling method is comprised of:
a first step for managing an empty address of the cell buffer memory, and for outputting the empty address as a buffer address to the cell buffer memory upon receipt of the storage request issued from the ATM cell managing means;
a second step for managing the buffer addresses in such a manner that while xe2x80x9cL (symbol xe2x80x9cLxe2x80x9d being an arbitrary natural number)xe2x80x9d pieces of storage areas capable of storing the buffer addresses are defined as one page, a chain structure is formed by chaining a plurality of the pages to each other and is made in correspondence with each of the output ports; upon receipt of the storage request issued from the cell managing means and also the buffer addresses transmitted from the first step, the received buffer addresses are sequentially stored into the storage area of the page of the chain structure; and
a third step for managing the buffer addresses in such a way that when the output request and the destination information issued from the ATM cell managing means are received, the buffer address managing means sequentially reads out the corresponding buffer address from the storage area of the page of chain structure corresponding to the received destination information to thereby transmit the read buffer address to both the cell buffer memory and the empty address managing means; wherein:
the buffer address read at the third step is managed at the first step.
Furthermore, an ATM switch circuit controlling method, according to a ninth aspect of the present invention, is featured by such a method for controlling an ATM (Asynchronous Transfer Mode) switch circuit, comprising:
a first step for producing a storage request of an inputted ATM cell and destination information indicative of an output port corresponding to the destination of the inputted ATM cell;
a second step for producing an output request and destination information when the ATM cell is outputted;
a third step for storing thereinto the ATM cell processed at the first step, while xe2x80x9cLxe2x80x9d pieces of storage areas capable of storing the ATM cells are defined as one page, by chaining the pages to each other so as to form a chain structure and also by employing the respective chain structures corresponding to the respective output ports, and also for reading the ATM cell to send the read ATM cell to the second step; and
a fourth step for controlling such that the ATM cells processed at the first step are sequentially stored into the chain structure corresponding to the destination information, when the storage request and the destination issued from the first step are received; wherein:
when both the output request and the destination information issued from the second step are received, the ATM cells are sequentially read from the chain structure corresponding to the destination information to execute the process operation defined at the second step with respect to said read ATM cells.